IP Solutions | Browse IP by Function
| Key ASIC provides value-added Intellectual Property (IP) libraries to facilitate customer's ASIC / SOC development and meet their application needs, as well as shorten the product's time-to-market. KA IP List By Function
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ARM9 Harden Macro Core
ARM9 Harden Core - SoCs for .13u CMOS
Description
With Key ASIC IP and Silterra CL130G process technology,
your designs will achieve the highest performance and
lowest cost in the industry. Key ASIC’s portfolio of
silicon verified IP provides all of the IO, CPU, and
analog functions required for your next multimedia or
wireless design.
your designs will achieve the highest performance and
lowest cost in the industry. Key ASIC’s portfolio of
silicon verified IP provides all of the IO, CPU, and
analog functions required for your next multimedia or
wireless design.
Features
a) Supports 1.8 volt, 2.5 volt and 3.3 volt interfaces.
b) Single polysilicon layer and up to eight (8) layers
of metal.
c) Gate delays: 20ps nom.
d) Compilable single port, dual port, ROM and register
files.
e) Flexible IO rings ~ inline and standard.
f) Low jitter PLL and DLL solutions.
g) Industry standard logical libraries.
h) Verified IP Iibraries for consumer and wireless
applications.
i) Leading high performance interfaces including PCI
Express and Serial ATA.
j) High performance ARM926 & ARM946 available
b) Single polysilicon layer and up to eight (8) layers
of metal.
c) Gate delays: 20ps nom.
d) Compilable single port, dual port, ROM and register
files.
e) Flexible IO rings ~ inline and standard.
f) Low jitter PLL and DLL solutions.
g) Industry standard logical libraries.
h) Verified IP Iibraries for consumer and wireless
applications.
i) Leading high performance interfaces including PCI
Express and Serial ATA.
j) High performance ARM926 & ARM946 available
ARM9 Harden Core - SoCs for .18u CMOS
Description
With Key ASIC IP and Silterra CL180G process
technology, your designs will achieve highest
performance and lowest cost in the industry.
Key ASIC’s portfolio of silicon verified IP
provides all the IO, CPU, and analog functions
required inyour next multimedia or wireless
design requirements.
technology, your designs will achieve highest
performance and lowest cost in the industry.
Key ASIC’s portfolio of silicon verified IP
provides all the IO, CPU, and analog functions
required inyour next multimedia or wireless
design requirements.
Features
a) Supports 1.8v and 3.3v supplies.
b) Single poly, up to 6 layers metal.
c) Gate delays: 25ps nom.
d) Compilable 1 port, dual port, ROM and
register files.
e) Flexible IO rings (inline, staggered).
f) Low jitter PLL and DLL
g) Industry standard standard cell libraries.
h) Verified IP Iibraries for consumer and
wireless applications.
i) 1.8 / 3.3 volt options.
b) Single poly, up to 6 layers metal.
c) Gate delays: 25ps nom.
d) Compilable 1 port, dual port, ROM and
register files.
e) Flexible IO rings (inline, staggered).
f) Low jitter PLL and DLL
g) Industry standard standard cell libraries.
h) Verified IP Iibraries for consumer and
wireless applications.
i) 1.8 / 3.3 volt options.
